This invention relates, in general, to semiconductor processing, and in particular, to semiconductor processes using dry etching and arsenic doping techniques.
Dry etching techniques including reactive ion etching (RIE), magnetron reactive ion etching (MRIE), plasma etching (PE), ion beam etching (IBE), electron cyclotron resonance (ECR) etching and, reactive ion beam etching (RIBE) are well known in the semiconductor industry. Dry etching is an important process for pattern transfer during the manufacture of integrated circuit devices.
Dry etching techniques can have a detrimental effect on a material being etched, on subsequent processing steps, and ultimately on integrated circuit device performance. These detrimental effects include residue layers, impurity and hydrogen permeation layers, bonding damage layers, surface roughening, and charge build-up damage. Known techniques for reducing impurity permeation layers such as Fe, Ni, Al, Na, Cr, K, and/or Zn impurity permeation layers include eliminating impurity sources and post-etch cleaning techniques. Annealing is a known technique for reducing bonding damage layers.
Field-effect transistor (FET) devices including metal oxide semiconductor FET (MOSFET) devices are also well known. Threshold voltage is an important electrical parameter of MOSFET devices that is often affected by processing problems associated with device fabrication. In general, the threshold voltage is a minimum gate voltage required before conduction occurs between a source electrode and a drain electrode. MOSFET based integrated circuit devices such as electrically erasable programmable read-only memory (EEPROM) devices utilize dry etching techniques at various stages of manufacture. In smaller geometry EEPROM devices, it is desirable to use arsenic as one dopant species in device fabrication because, among other things, arsenic diffuses at a slower rate than phosphorous. However, when dry etching techniques are used with arsenic doped devices such as smaller geometry EEPROM devices, significant shifts can occur in the threshold voltage parameter. Thus, a need exists for a method for reducing threshold voltage shifts in arsenic doped devices where dry etching techniques are used.